Name Last modified Size Description
Parent Directory - Makefile 2022-12-06 00:16 384 err1.eqn 2022-12-06 00:16 377 err2.eqn 2022-12-06 00:16 376 expr.eqn 2022-12-06 00:16 35 expr3.eqn 2022-12-06 00:16 53 gal22v10.c 2022-12-06 00:16 9.3K gal22v10.c.html 2022-12-06 00:16 12K maketable.c 2022-12-06 00:16 19K maketable.c.html 2022-12-06 00:16 27K max.eqn 2022-12-06 00:16 375 not.eqn 2022-12-06 00:16 83
GAL22V10.c is a first draft of a simulator for GAL22V10 chips as used in the 6809 Max board I'm assembling. I'm also experimenting with code (maketable.c) to take a set of logic equations and convert them first to sum-of-products form (i.e. suitable for use in a Pla) and also to minimised logic equations, but eventually to a suitable configuration for a GAL22V10 chip that can be written to real hardware.
The GAL22V10 is not a simple Pla - the logic it supports is a bit convoluted. But it is more like a Pla than say a programmable gate array - each output term is basically the 'And' sum of multiple input terms. The output can be optionally inverted and also optionally latched on rising 'Clk'. It's not clear yet if all the input pins can also be optionally inverted - you would hope that was the case but I haven't found it in the documentation yet.