Name Last modified Size Description
Parent Directory - 22v10.pdf 2005-09-30 08:44 303K minimo.c.html 2026-01-14 14:09 59K tens.mtg 2026-01-14 14:06 59K minimo.c 2026-01-14 14:09 42K palwiz-1.3a2.zip 2020-01-07 22:38 42K plamin.pas.html 2026-01-12 17:41 36K minimo.imp.html 2026-01-13 23:58 36K DOC0434.PDF 2024-07-15 02:06 30K maketable.c.html 2022-12-06 00:16 27K minimo.imp 2026-01-13 23:53 24K plamin.pas 2026-01-12 17:41 19K maketable.c 2022-12-06 00:16 19K gal22v10.c.html 2022-12-06 00:16 12K gal22v10.c 2022-12-06 00:16 9.3K Makefile 2022-12-06 00:16 384 err1.eqn 2022-12-06 00:16 377 err2.eqn 2022-12-06 00:16 376 max.eqn 2022-12-06 00:16 375 SEE_ALSO.txt 2026-01-12 17:46 176 test.mtb 2026-01-13 23:28 99 not.eqn 2022-12-06 00:16 83 test-tab.mtb 2026-01-14 14:05 81 expr3.eqn 2022-12-06 00:16 53 expr.eqn 2022-12-06 00:16 35 palwiz/ 2026-01-12 17:36 -
GAL22V10.c is a first draft of a simulator for GAL22V10 chips as used in the 6809 Max board I'm assembling. I'm also experimenting with code (maketable.c) to take a set of logic equations and convert them first to sum-of-products form (i.e. suitable for use in a Pla) and also to minimised logic equations, but eventually to a suitable configuration for a GAL22V10 chip that can be written to real hardware.
The GAL22V10 is not a simple Pla - the logic it supports is a bit convoluted. But it is more like a Pla than say a programmable gate array - each output term is basically the 'And' sum of multiple input terms. The output can be optionally inverted and also optionally latched on rising 'Clk'. It's not clear yet if all the input pins can also be optionally inverted - you would hope that was the case but I haven't found it in the documentation yet.