! simulator for 8080/8085 machine instruction set
%routine simulate(%integer PC)
%integer opc
%switch sw(0:255)
%cycle
  opc = bfetch(PC)

  %if opc&2_1100 0000 = 2_0100 0000 %start
    ! 01XX XXXX 64..127  MOV d, s
    
    %continue
  %finish %else -> sw€°IMP_PRINT_HEX	 €ÿ	 IMP_CONDITION_HANDLER	 
IMP_X_TO_S	 IMP_PRINT_STRING         c ç     ‚ €ç          ÿÿÿÿÿÿÿ   €¨'Ælx'Þ€Ý|_Àl_88>tÎÆpN¦üÅp   	z	'†p7pê'†p0pÇl×ÁlÇÇpl×ÁtÇ¡   GÀÊßÀêÅ   ÿz'®€ÿN#Æ010): ! ADC 2
sw(2_10001011): ! ADC 3
sw(2_10001100): ! ADC 4
sw(2_10001101): ! ADC 5
sw(2_10001110): ! ADC 6
sw(2_10001111): ! ADC 7
  EA == bytereg(0); -> adc
sw(16_8E): ! ADC M
  EA == mem
adc:
  %continue
{--------------------------------- ADD --------;11985-02-01 12:13:14-SIA1:[IMPRTL.PANOS.SOURCE.SYSTEM]FREEST.IMP;1Lattice Logic IMP 9.12-2.27-2.4 IMP_FREE_STORE	 (	 IMP_CONDITION_HANDLER	  LL___HEAP_BASE         €… (     ‚ '¾|À|#° ’ 2 ‚€ ×Å×Å×Å×Å"’2(( 6): ! ADD M
  EA == mem; -> add
sw(16_C6): ! ADI
  EA == imm
add:
  %continue
{--------------------------------- AND ------------------------------------}
sw(2_10100000): ! ANA 0
sw(2_10100001): ! ANA 1
sw(2_10100010): ! ANA 2
sw(2_10100011): ! ANA 3
sw(2_MTIME€ÔIMP_CPU_TIME	 		 IMP_CONDITION_HANDLER	 DATE	 TIME	 STANDARDTIME         ™ ò    7 ‚ €HçÅxç­?çÅ¿¹"| z_ÀxÆx¿¸—ÀgÀ¿¹ÎH×  8’ 277 ‚ €HçÅxç­?çÅ¿¹"| z_ÀxÆx¿¸—ÀgÀ¿¹ÎH×  8’ 2n( ‚ €HçÅxç­?çÅ¿¹"----------------------}
sw(16_CD): ! CALL
  %continue
sw(16_DC): ! CC
  %continue
sw(16_FC): ! CM
  %continue
sw(16_D4): ! CNC
  %continue
sw(16_C4): ! CNZ
  %continue
sw(16_F4): ! CP
  %continue
sw(16_EC): ! CPE
  %continue
sw(16_E4): ! CPO
  %continue
swL.PANOS.SOURCE.SYSTEM]LLTRANS.IMP;11985-02-01 12:13:14.SIA1:[IMPRTL.PANOS.SOURCE.SYSTEM]LLTRANS.IMP;1Lattice Logic IMP 9.12-2.27-2.4X LL_TRANSLATE	 €m	 IMP_CONDITION_HANDLER	 GETGLOBALSTRING         €Ç m    X ‚ ‚ÎÀWÀ§À¿”---------------- CMP ------------------------------------}
sw(2_10111000): ! CMP 0
  %continue
sw(2_10111001): ! CMP 1
  %continue
sw(2_10111010): ! CMP 2
  %continue
sw(2_10111011): ! CMP 3
  %continue
sw(2_10111100): ! CMP 4
  %continue
sw(2_10111101): ! CMP 5
  %continue
sw(2_10111110): ! CMP 6
  %continue
sw(2_10111111): ! CMP 7
  %continue
sw(16_BE): ! CMP M
  %continue
sw(16_FE): ! CPI
  %continue
{--------------------------------- DAA ------------------------------------}
sw(16_27): ! DAA
  %continue! simulator for 8080/8085 machine instruction set
%routine simulate(%integer PC)
%integer opc
%switch sw(0:255)
%cycle
  opc = bfetch(PC)

  %if opc&2_1100 0000 = 2_0100 0000 %start
    ! 01XX XXXX 64..127  MOV d, s
    
    %continue
  %finish %else -> sw DEC ------------------------------------}
sw(2_00000101): ! DCR 0
  %continue
sw(2_00001101): ! DCR 1
  %continue
sw(2_00010101): ! DCR 2
  %continue
sw(2_00011101): ! DCR 3
  %continue
sw(2_00100101): ! DCR 4
  %continue
sw(2_00101101): ! DCR 5
  %contin010): ! ADC 2
sw(2_10001011): ! ADC 3
sw(2_10001100): ! ADC 4
sw(2_10001101): ! ADC 5
sw(2_10001110): ! ADC 6
sw(2_10001111): ! ADC 7
  EA == bytereg(0); -> adc
sw(16_8E): ! ADC M
  EA == mem
adc:
  %continue
{--------------------------------- ADD ------------------------------------ DI ------------------------------------}
sw(16_F3): ! DI
  %continue
sw(16_FB): ! EI
  %continue
{---------------------------------     ------------------------------------}
sw(16_76): ! HLT
  %continue
{--------------------------------- IN  ------------------------------------}
sw(16_DB): ! IN
  %continue
sw(16_D3): ! OUT
  %continue
{--------------------------------- INC ------------------------------------}
sw(2_00000100): ! INR 0
  %continue
sw(2_00001100): ! INR 1
  %continue
sw(2_00010100): ! INR 2
  %continue
sw(2_00011100): ! INR 3
  %continue
sw(2_00100100): ! INR 4
  %continue
sw(2_00101100): ! INR 5
  %continue
sw(2_00110100): ! INR 6
  %continue
sw(2_00111100): ! INR 7
  %continue
sw(16_34): ! INR M
  %continue
sw(2_00000011): ! INX 0
  %continue
sw(2_00010011): ! INX 1
  %continue
sw(2_00100011): ! INX 2
  %continue
sw(2_00110011): ! INX 3
  %continue
{--------------------------------- JMP ------------------------------------}
sw(16_DA): ! JC
  %continue
sw(16_FA): ! JM
  %continue
sw(16_C3): ! JMP
  %continue
sw(16_D2): ! JNC
  %continue
sw(16_C2): ! JNZ
  %continue
sw(16_F2): ! JP
  %continue
sw(16_EA): ! JPE
  %continue
sw(16_E2): ! JPO
  %continue
sw(16_CA): ! JZ
  %continue
sw(16_E9): ! PCHL
  %continue
{------------------------- CMP ------------------------------------}
sw(2_10111000): ! CMP 0
  %continue
sw(2_10111001): ! CMP 1
  %continue
sw(2_10111010): ! CMP 2
  %continue
sw(2_10111011): ! CMP 3
  %continue
sw(2_10111100): ! CMP 4
  %continue
sw(2_10111101): ! CMP 5
  %continue
sw(2_10111110): ! CMP 6
  %continue
sw(2_10111111): ! CMP 7
  %continue
sw(16_BE): ! CMP M
  %continue
sw(16_FE): ! CPI
  %continue
{--------------------------------- DAA ------------------------------------}
sw(16_27): ! DAA
  %continue): ! MOV M, 4
  %continue
sw(2_01110101): ! MOV M, 5
  %continue
sw(2_01110110): ! MOV M, 6
  %continue
sw(2_01110111): ! MOV M, 7
  %continue
sw(2_00000110): ! MVI 0
  %continue
sw(2_00001110): ! MVI 1
  %continue
sw(2_00010110): ! MVI 2
  %continue
sw(2_00011110): ! MVI 3
  %continue
sw(2_00100110): ! MVI 4
  %continue
sw(2_00101110): ! MVI 5
  %continue
sw(2_00110110): ! MVI 6
  %continue
sw(2_00111110): ! MVI 7
  %continue
sw(16_36): ! MVI
  %continue
sw(16_32): ! STA
  %continue
sw(2_00000010): ! STAX 0
  %continue
sw(2_00010010): ! STAX 1
  %continue
{--------------------------------- NOP ------------------------------------}
{---------------------------------     ------------------------------------}
sw(0): ! NOP
  %continue
{--------------------------------- OR ------------------------------------}
sw(2_10110000): ! ORA 0
  %continue
sw(2_10110001): ! ORA 1
  %continue
sw(2_10110010): ! ORA 2
  %continue
sw(2_10110011): ! ORA 3
  %continue
sw(2_10110100): ! ORA 4
  %continue
sw(2_10110101): ! ORA 5
  %continue
sw(2_10110110): ! ORA 6
  %continue
sw(2_10110111): ! ORA 7
  %continue
sw(16_B6): ! ORA M
  %continue
sw(16_F6): ! ORI
  %continue
{--------------------------------- POP ------------------------------------}
sw(2_11000001): ! POP 0
  %continue
sue
sw(2_00010100): ! INR 2
  %continue
sw(2_00011100): ! INR 3
  %continue
sw(2_00100100): ! INR 4
  %continue
sw(2_00101100): ! INR 5
  %continue
sw(2_00110100): ! INR 6
  %continue
sw(2_00111100): ! INR 7
  %continue
sw(16_34): ! INR M
  %continue
sw(2_0--------------------------------- ROT ------------------------------------}
sw(16_17): ! RAL
  %continue
sw(16_1F): ! RAR
  %continue
sw(16_0F): ! RRC
  %continue
sw(16_07): ! RLC
  %continue
{--------------------------------- RET -------------------------JM
  %continue
sw(16_C3): ! JMP
  %continue
sw(16_D2): ! JNC
  %continue
sw(16_C2): ! JNZ
  %continue
sw(16_F2): ! JP
  %continue
sw(16_EA): ! JPE
  %continue
sw(16_E2): ! JPO
  %continue
sw(16_CA): ! JZ
  %continue
sw(16_E9): ! PCHL
  %continue
{---------Z
  %continue
{--------------------------------- RIM ------------------------------------}
sw(16_20): ! RIM
  %continue
sw(16_30): ! SIM
  %continue
{--------------------------------- RST ------------------------------------}
sw(2_11000111): ! RST 0  scaled ?
  %continue
sw(2_11001111): ! RST 1
  %continue
sw(2_11010111): ! RST 2
  %continue
sw(2_11011111): ! RST 3
  %continue
sw(2_11100111): ! RST 4
  %continue
sw(2_11101111): ! RST 5
  %continue
sw(2_11110111): ! RST 6
  %continue
sw(2_11111111): ! RST 7
  %continue
{--------------------------------- SBB ------------------------------------}
sw(2_10011000): ! SBB 0
  %continue
sw(2_10011001): ! SBB 1
  %continue
sw(2_10011010): ! SBB 2
  %continue
sw(2_10011011): ! SBB 3
  %continue
sw(2_10011100): ! SBB 4
  %continue
sw(2_10011101): ! SBB 5
  %continue
sw(2_10011110): ! SBB 6
  %continue
sw(2_10011111): ! SBB 7
  %continue
sw(16_9E): ! SBB M
  %continue
sw(16_DE): ! SBI
  %continue
{--------------------------------- SHLD -----------------------------------0
  %continue
sw(2_00010010): ! STAX 1
  %continue
{--------------------------------- NOP ------------------------------------}
{---------------------------------     ------------------------------------}
sw(0): ! NOP
  %continue
{------------------------------------------------ SUB ------------------------------------}
sw(2_10010000): ! SUB 0
  %continue
sw(2_10010001): ! SUB 1
  %continue
sw(2_10010010): ! SUB 2
  %continue
sw(2_10010011): ! SUB 3
  %continue
sw(2_10010100): ! SUB 4
  %continue
sw(2_10010%continue
sw(2_10110110): ! ORA 6
  %continue
sw(2_10110111): ! ORA 7
  %continue
sw(16_B6): ! ORA M
  %continue
sw(16_F6): ! ORI
  %continue
{--------------------------------- POP ------------------------------------}
sw(2_11000001): ! POP 0
  %continue
s%continue
{--------------------------------- XOR ------------------------------------}
sw(2_10101000): ! XRA 0
  %continue
sw(2_10101001): ! XRA 1
  %continue
sw(2_10101010): ! XRA 2
  %continue
sw(2_10101011): ! XRA 3
  %continue
sw(2_10101100): ! XRA 4
 --------------------------------- ROT ------------------------------------}
sw(16_17): ! RAL
  %continue
sw(16_1F): ! RAR
  %continue
sw(16_0F): ! RRC
  %continue
sw(16_07): ! RLC
  %continue
{--------------------------------- RET -------------------------sw(16_E3): ! XTHL
  %continue
%repeat
%end
%endoffile