this is excerpted from an email to a friend I sent when the 6809 started working...

Its a pretty simple design.  30ns Rom for address decoding/timing signals, &
Mega-neat flat-pack 64k Ram.  Tubes (r) don't half make life easier.
I'll use exactly the same logic as I have on the board just now as my first
chip when we do our test run next month.  The address decode is a
function with 8 inputs & four outputs, and should really be in a PLA -
I just used a Rom because we have no FPLAs/PALs.  There's currently four
'153s on the board for the bus-folding - although 2 input mux's would have
done. I just wasn't sure if my figures for software refresh were correct so
I left my options open. All I need for dead-cycle refresh is an 8-bit counter.