Contents

The DL1 gate level simulator
...uses .................................................. 1
...three valued simulation ............................... 1
...interpretation of the third logic value ............... 1
...pessimism and optimism ................................ 1
...the two phases of SIM ................................. 1
...simulating power up ................................... 1
...simulating the circuit's dynamic behaviour ............ 2
...detecting potential problems .......................... 2

Using SIM on VAX
...accessing SIM ......................................... 2
...getting HELP information .............................. 2
...gates recognised by SIM ............................... 2
...default extensions for filenames ...................... 3
...POSTPRO - producing timing diagrams ................... 3
...examples .............................................. 3

Driving the simulator
...simulator subcommands ................................. 3
......HELP ............................................... 3
......INPUTS? ............................................ 3
......OUTPUTS? ........................................... 4
......ALL ................................................ 4
......SET ................................................ 4
......GO ................................................. 4
......VAL ................................................ 4
......STOP ............................................... 4
......HOLD ............................................... 4
......FREE ............................................... 4
......XS ................................................. 4
...interpretation of phase 1's output .................... 4

Driving the second phase of the simulator
...setting up input stimuli .............................. 5
......DEFINE ............................................. 5
......LET ................................................ 5
...examples .............................................. 5
...conditional input stimuli ............................. 6
......WHEN ............................................... 6
...conditions ............................................ 6
...examples .............................................. 6
...editing sets of stimuli ............................... 6
......SHOW ............................................... 6
......DELTRACE ........................................... 6

Starting the second phase of the simulation
...RUN ................................................... 6
......default delays ..................................... 6
......simulation time limit .............................. 7
......optimistic or pessimistic simulation ............... 7


The gate model

The extension to ROM and RAM ............................. 7
...labeling memories ..................................... 7
...default values for memories ........................... 7
...interpretation of signals ............................. 7
...an example ............................................ 8
...initialising a memory ................................. 8
......FILL ............................................... 8

References

An example of the use of SIM ............................. 9
...the Johnson counter ................................... 9
...the dialogue with VAX, SIM, and POSTPRO ............... 9
......compiling the description .......................... 9
......flattening the description ......................... 9
......the dialogue with SIM .............................. 9
......the dialogue with POSTPRO .......................... 9

POSTPRO's output ......................................... 10
...the header page ....................................... 10
...the timing diagram .................................... 11


Introduction

Using SIM on VAX

Examples:

SIM JCOUNT                {JCOUNT.FIC/JCOUNT.TRC is assumed}
SIM ADDER/.N              {only the first phase of the simulator is used on ADDER.FIC}
SIM COMB.EIC/.N           {very simple circuit - doesn't need flattening so use compiler output .EIC}

POSTPRO JCOUNT            {produce timing diagram in JCOUNT.WVM}
POSTPRO JCOUNT/.LIS       {produce timing diagram in JCOUNT.LIS}

Driving the simulator

INPUTS? causes a list of the names of circuit inputs to be printed at the terminal.

VAL <name> {[,]<name>}* causes the values of the named outputs to be printed at the terminal.

STOP stop the simulator and return to system command level.

Driving the second phase of the simulator

trace    ::= {tel}*
tel      ::= ( trace ) {count}
            @ tracename
            value {length}
value    ::= L | R | H | F

DEFINE <name> = <trace> {, <name> = <trace>}*

Signal traces are associated with inputs by using the LET subcommand:

LET <name> = <trace> {, <name> = <trace>}*

Examples:

DEFINE PULSE = L10 R5 H50 F5 L10
LET A<0> = (@PULSE)10
LET A<1> = (L10 (L10 R5 H50 F5)5 L100)*
LET ACK' = H200 F L

WHEN <condition> LET ...

WHEN CLK=1 & ENBL'=0 & SIGNAL=1
LET SIGNAL = F5 (TESTPULSE)10 TESTPULSE starts from 0

SHOW { <name> {[,] <name>}* }

DELTRACE { <name> {[,] <name>}* }

Starting the second phase of the simulation

The gate model

The extension to ROM and RAM

ROM1: ROM(ADDRESS<0:3>, SEL)->DATA<0:3>

MEM1:RAM(ADDR<0:3>,DIN<0:7>,RW,SEL)->DOUT<0:7>

declares a 16 byte random access memory called MEM1. ROMs and RAMs are initialised by means of the FILL subcommand:

FILL <memory-name> FROM <filename>

References

[CHIC76] C Chicoix, J Pedoussat and N Giambiasi
An accurate time delay model for large digital network simulation.
13th ACM/IEEE Design Automation Conference Proceedings, pp42-47, 1976.

[EICH65] E B Eichelberger
Hazard detection in combinatorial and sequential switching circuits.
IBM Journal of Research and Development, March 1965.

A worked example

UNIT JCOUNT(CK,CL)->D1,D2,D3,D4
    UNIT DFF(P,CK,D,CL)->Q,QB
        NAND(J,P,KB)->JB
        NAND(CK,JB,CL)->J
        NAND(CK,KB,J)->K
        NAND(D,K,CL)->KB
        NAND(J,QB,P)->Q
        NAND(K,Q,CL)->QB
    END

    DFF(.1,CK,DO,CL)->D1,?
    DFF(.1,CK,D1,CL)->D2,?
    DFF(.1,CK,D2,CL)->D3,?
    DFF(.1,CK,D3,CL)->D4,?
    NOT(D4)->DO
END

The dialogue with VAX and SIM proceeds as follows:

$ esdl jcount                {compile the description}
$ flatten jcount             {and flatten it}
$ sim jcount                 {invoke the simulator output to jcount.trc}

SIM version 4.0 (VAX)

Circuit initialisation (Eichelberger)

-> inputs?                   {enquire the names of circuit inputs}
    CK CL                    {there are two - CK and CL}
-> all 0                     {set all inputs to 0}
-> go                        {and evaluate the circuit}
    X X X X                  {outputs with inputs uncertain}
    0 0 0 0                  {outputs with inputs 0}
-> set cl=1                  {stop asserting clear signal}
-> go
    0 0 0 0
    0 0 0 0
    0 0 0 0
-> let ck=(140 r5 h80 f5 140)20   {set up a signal trace connected to CK}
-> run                       {and start the second phase running}
Default delays 5 10 3 6      {5 10 3 6 supplied by the user}
Simulat'n time 1000          {replied to prompt with 1000}
Random delays? y             {choose optimistic simulation}
Random no seed 1234          {1234 chosen as seed}
*End of simulation           {SIM has done it in no time!}
$ postpro john               {produce the waveform trace}
Width of page= 60            {print output in 60 columns}
Signal names ck d1 d2 d3 d4  {trace clock and outputs only}
Signal names *               {'* to end the list}
Compr'n factor=3             {remove all inactive periods of len<3}

Output from POSTPRO

Simulation of circuit JCOUNT by SIM version 4.0 (VAX)

Circuit inputs at start of simulation:-

CK=0
CL=1

Signal traces attached to circuit inputs:-

CK=(L40 R5 H80 F5 L40)20