{ A test program testing all the modules of ILAP }

Program testall (input,output);

Const
   %include 'nmos.consts'

Type
   %include 'nmos.types'

%Include 'nmos.specs'

Procedure RAM %alias 'ILAP_RAM' (X, Y:integer);extern;

Procedure starttest (name:string[63]);
   
   Var i :integer;

   Begin
      writeln;
      For i := 1 to 72 do write ('#');
      writeln;
      writeln;
      writeln (name);
      writeln;
   End;


{###############################################################################}
{#                                                                             #}
{#      T E S T  1  :  A test of the ILAP contact symbols                      #}
{#                                                                             #}
{###############################################################################}


Procedure test1;
begin
   starttest ('The ILAP Contact symbols');
   symbol ('contacts');
      pdbns (10, 10);
      pdbew (20, 10);
      pdbn  (0, 20);
      pdbs  (10, 20);
      pdbe  (20, 20);
      pdbw  (30, 20);
      pdcn  (0, 30);
      pdcs  (10, 30);
      pdce  (20, 30);
      pdcw  (30, 30);
      pdmn (0, 0);
      pdms (10, 0);
      pdme (20, 0);
      pdmw (30, 0);
      pm (10, 40);
      dm (20, 40);
   endsymbol;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  2  :  A test of all the types of ILAP transistor              #}
{#                                                                             #}
{###############################################################################}

Procedure test2;
begin
   starttest ('The ILAP transistors');
   symbol ('transistors');
      DTDBX ('Dep Tran Diff Bur X', 8, 8, 16);
      DTDX ('Dep Tran Diff X', 4, 18, 9);
      DTDY ('Dep Tran Diff Y', 26, 18, 2);
      DTPX ('Dep Tran Poly X', 4, 28, 9);
      DTPY ('Dep Tran Poly Y', 26, 28, 2);
      ETDX ('Enh Tran Poly X', 4, 38, 9);
      ETDY ('Enh Tran Poly Y', 26, 38, 2);
      ETPX ('Enh Tran Poly X', 4, 48, 9);
      ETPY ('Enh Tran Poly Y', 26, 48, 2);
   endsymbol;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  3  :  A shift register + test of the DRC                      #}
{#                                                                             #}
{###############################################################################}

Procedure test3;

   Procedure makeshiftregister (number:integer);
      Var loopcount:integer;
   Begin
      SYMBOL ('shift register');
         for loopcount := 1 to  number do begin
              DRAW ('shift cell', SX ('shift cell') * (loopcount - 1), 0);
         end;
      ENDSYMBOL;
   End;

begin

   starttest ('A sample ILAP program with design rule checking');
   DRCON;

   SYMBOL ('inverter');
      ETPX ('ET', 2, 5, 6);   { Enhancement transistor at (2,5) of length 6 }
      DTDBY ('DT', 4, 11, 7); { Depletion transistor including contact }
      DM (5, 2);              { Diffusion to Metal contact for GND }
      DM (5, 21);             { Diffusion to Metal contact for VDD }
      LAYER (METAL);  WIDTH (4);
      GNDWIREX (0, 0, 10);
      VDDWIREX (0, 19, 10);
      LAYER (DIFFUSION);
      WIREX (6, 8, 4);        { Output line }
   ENDSYMBOL;

   SYMBOL ('pass transistor');
      ETDX ('PT', 2, 8, 2);  { The pass transistor }
      LAYER (METAL);   WIDTH (4);
      GNDWIREX (0, 0, 6);
      VDDWIREX (0, 19, 6);
      LAYER (POLY);
      WIREY (2, 0, 26);       { Clock line }
   ENDSYMBOL;

   SYMBOL ('interface cell');
      PDBW (3, 9);            { Change from diffusion to poly for next stage }
      LAYER (POLY);
      WIREX (2, 5, 4);
      LAYER (METAL);   WIDTH (4);
      GNDWIREX (0, 0, 6);
      VDDWIREX (0, 19, 6);
   ENDSYMBOL;

   SYMBOL ('shift cell');
      DRAW ('inverter', 0, 0);
      DRAW ('pass transistor', SX ('inverter'), 0);
      DRAW ('interface cell', SX ('inverter') + SX ('pass transistor'), 0);
   ENDSYMBOL;

   makeshiftregister (4);
   DRCOFF;
End;

{###############################################################################}
{#                                                                             #}
{#      T E S T  4  :  A test of the PLA generators                            #}
{#                                                                             #}
{###############################################################################}

Procedure test4;

Var
   a, b : integer;
   pin, pout : array [1..10] of integer;
   null : array [1..1] of integer;
   is   : array [1..3] of integer;
   os   : array [1..5] of integer;

begin
   is[1] := bottom ; is[2] := top; is[3] := bottom;
   os[1] := bottom; os[2] := top; os[3] := top; os[4] := bottom;os[5]:=bottom;

   starttest ('A test of the PLA generators');
   tpla ('Pla Normal', 'pla', a, b, pin, pout);

   stpla ('Pla Top Out', 'pla', topoutputs, null, null, a, b, pin, pout);

   stpla ('Pla Top In', 'pla', topinputs, null, null, a, b, pin, pout);

   { Set up positions for inputs and outputs }
   for a := 1 to 3 do pin[a]  := 35 + (a-1)*20;
   for a := 1 to 5 do pout[a] := 150 + (a-1)*20;

{   sepla ('Pla Stretch', 'pla', stretch, null, null, a, b, pin, pout);}

{   sepla ('Pla Mixed', 'pla', mixedinputs+mixedoutputs+stretch,
          is, os, a, b, pin, pout);}
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  5  :  A test of the ROM generator                             #}
{#                                                                             #}
{###############################################################################}

Procedure test5;

Var
   a, b : integer;
   pin, pout : array [1..50] of integer;
begin
   starttest ('A test of the ROM generator');
   rom ('rom', 'rom', a, b, pin, pout);
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  6  :  A test if the Stack generator                           #}
{#                                                                             #}
{###############################################################################}

Procedure test6;
   Procedure dostack (b, w :integer; s : string[31]);
      Var
         stx,sty, cox, coy, pux, pox, p1y, p2y, p3y, p4y:integer;
         puy, poy : array [1..10] of integer;
         i : integer;
   Begin
  {%option '-code'}
      stack(s, b, w, cox, coy, pux, pox, p1y, p2y, p3y, p4y, puy, poy);
   end;

begin
   starttest ('A test of the Stack generator');
   dostack (1, 1, 'S11');
   dostack (1, 2, 'S12');
   dostack (1, 3, 'S13');
   dostack (2, 4, 'S24');
   dostack (4, 2, 'S42');
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  7  :  A test if the Counter generator                         #}
{#                                                                             #}
{###############################################################################}

Procedure test7;

   Const
      maxn = 16;

   Var
      suby, loady, vddy, phi2y, phi1y, gndy, i:integer;
      ins, outs, outsb : array [1..maxn] of integer;

begin
   starttest ('A test of the Counter generator');
   counter ('counter 3', 3, suby, loady, vddy,
             phi1y, phi2y, gndy, ins, outs, outsb);
   Write ('   Sub Y   = ',suby:3,'   ');
   Write ('   Load Y  = ',loady:3,'   ');
   Writeln ('   VDD Y   = ',vddy:3);
   Write ('   Gnd Y   = ',gndy:3,'   ');
   Write ('   Phi1 Y  = ',phi1y:3,'   ');
   Writeln ('   Phi2 Y  = ',phi2y:3);
   Write ('   IN s  : ');
   for I := 1 to 3 do write (ins[i]:4);
   writeln;
   Write ('   Outs  : ');
   for I := 1 to 3 do write (outs[i]:4);
   writeln;
   Write ('   Outsb : ');
   for I := 1 to 3 do write (outsb[i]:4);
   writeln;
   counter ('counter 4', 4, suby, loady, vddy, phi1y, phi2y,
             gndy, ins, outs, outsb);
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  8  :  A test of the RAM generator                             #}
{#                                                                             #}
{###############################################################################}

Procedure test8;

   Var
      X, Y : integer;
      pin,pout: array [1..50] of integer;
begin
   starttest ('A test of the RAM generator');
   ram (6, 3);
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  9  :  A test of the ILAP river-router                         #}
{#                                                                             #}
{###############################################################################}

Procedure Test9;
   
   Const
      mwid=3;       { metal line width}
      msep=3;       { metal line separation}

   Var
      a ,b : array [1..12] of port;
      i,sepn : integer;

begin
   starttest ('A test of the river-router');

   for i :=1 to 12 do begin
      a[i].x := 7*i+35;
      a[i].w := 4;
      b[i].x := 15*(i-1);
      b[i].w := 4;
   end;
   sepn := route ('river route', a, b, 12, metal, mwid, msep, 0);

   symbol('river route demo');
      for i := 1 to 12 do pm (a[i].x+2, 1) ;
      draw ('river route', 0, 0);
      for i := 1 to 12 do dm (b[i].x+2, sepn-1);
   endsymbol;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  10  :  A test of the ILAP corner router                       #}
{#                                                                             #}
{###############################################################################}

Procedure test10;

   Const
      mwid = 3;    {metal width}
      msep = 3;    {metal separation}
   Var
      a, b : array [1..6] of port;
      i, ya, xb : integer;

begin
   starttest ('A test of the corner-router');

   ya := 0;
   xb := 100;
   for i := 1 to 6 do begin
     a[i].x := xb - 15*i;
     a[i].w := 4;
     b[i].x := ya + 12*i;
     b[i].w := 4;
   end;

   croute('corner route', a, b, 6, ya, xb, metal, mwid, msep);

   symbol('corner route demo');
     for i := 1 to 6 do pm(a[i].x+2, ya+1);
     draw('corner route', 0, 0);
     for i := 1 to 6 do dm(xb-1, b[i].x+2);
   endsymbol;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  11  :  A test of the ILAP side router                         #}
{#                                                                             #}
{###############################################################################}

Procedure test11;

   Const
      ac=6;ab=3;bc=4;cd=2;da=4;
      ya=0;xb=120;yc=80;xd=0;

   Var
      a : array [1..da+ac+ab] of port;
      b : array [1..ab+bc]    of port;
      c : array [1..cd+ac+bc] of port;
      d : array [1..da+cd]    of port;
      i,j,k,l: integer;

begin
   starttest ('A test of the side-router');

   for i := 1 to da+ac+ab do begin
      a[i].x := 8*i;
      a[i].w := 4;
   end;
   for i := 1 to ab+bc do begin
      b[i].x := 7*i;
      b[i].w := 3;
   end;
   for i := 1 to cd+ac+bc do begin
      c[i].x := 8*i;
      c[i].w := 3 ;
   end;
   for i := 1 to da+cd do begin
      d[i].x := 12*i;
      d[i].w := 4;
   end;

   sroute ('side route',a,b,c,d,ac,ab,bc,cd,da,ya,xb,yc,xd,metal,3,3);

   symbol('side route demo');
     draw('side route', 0, 0);
     for i := 1 to da+ac+ab do pm(a[i].x+2, ya+1);
     for i := 1 to ab+bc do dm(xb-1, b[i].x+1) ;
     for i := 1 to cd+ac+bc do pm(c[i].x+1, yc-1) ;
     for i := 1 to da+cd do dm(xd+1, d[i].x+2) ;
   endsymbol;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  12  :  A test of the ILAP channel router                      #}
{#                                                                             #}
{###############################################################################}

Procedure test12;
begin
   Writeln ('Not implemented');
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  13  :  A test of the ILAP bonding pad symbols                 #}
{#                                                                             #}
{###############################################################################}

Procedure test13;

   Var
      padinx, padoutx, padcloutx, padcloutclx : integer;
      padinoutinx, padinoutoutx, padinoutenx  : integer;

begin
   starttest ('A test of the bonding pads');
   padvdd;
   Write ('   Pad vdd     :  SX =',sx('padvdd'):2);
   Write ('    SY =',sy('padvdd'):3);
   writeln;writeln;
   
   padgnd;
   Write ('   Pad gnd     :  SX =',sx('padgnd'):2);
   Write ('    SY =',sy('padgnd'):3);
   Writeln; writeln;

   padin (padinx);
   Write ('   Pad in      :  SX =',sx('padin'):2);
   Write ('    SY =',sy('padin'):3);
   Write ('    X =',padinx:2);
   Writeln; Writeln; 

   padout (padoutx);
   Write ('   Pad out     :  SX =',sx('padout'):2);
   Write ('    SY =',sy('padout'):3);
   Write ('    X =',padoutx:2);
   Writeln; Writeln ;

   padclout (padcloutx, padcloutclx);
   Write ('   Pad cl out  :  SX =',sx('padclout'):2);
   Write ('    SY =',sy('padclout'):3);
   Write ('    X =',padcloutx:2);
   Write ('    CL X =',padcloutclx:2);
   Writeln ; Writeln ;

   padinout (padinoutinx, padinoutoutx, padinoutenx);
   Write ('   Pad in out  :  SX =',sx('padinout'):2);
   Write ('    SY =',sy('padinout'):3);
   Write ('    IN X =',padinoutinx:2);
   Write ('    OUT X =',padinoutoutx:2);
   Write ('    EN X =',padinoutenx:2);
   Writeln ;
end;

{###############################################################################}
{#                                                                             #}
{#      T E S T  14  :  A test of the automatic pad placement                  #}
{#                                                                             #}
{###############################################################################}

Procedure test14;

   Const
      dwid = 2; mwid = 8; { Diffusion and Metal widths }
      yh = 80; xsep = 50;
      chipno = 1;  { The CIF symbol number of the external symbol }
      maxport = 14;

   Var
      ports : array [1..maxport] of connf;
      i : integer;
begin
   starttest ('The ILAP Pad Placement routine');

   EXTERNALSYMBOLSPEC ('Chip',chipno, 0, 0, 6*xsep, yh);

   fillport (ports[1], vddpad, left, (yh div 2)-(mwid div 2), mwid, metal);
   for i := 1 to 5 do begin
      fillport (ports[i+1], inpad, top, i*xsep, dwid, diffusion);
   end;
   fillport (ports[7], gndpad, right, (yh div 2)-(mwid div 2), mwid, metal);
   fillport (ports[8], cloutpadcl, bottom, 5*xsep, dwid, diffusion);
   fillport (ports[9], cloutpad, bottom, 4*xsep, dwid, diffusion);
   fillport (ports[10], outpad, bottom, 3*xsep+(xsep div 2), dwid, diffusion);
   fillport (ports[11], inoutpaden, bottom, 3*xsep, dwid, diffusion);
   fillport (ports[12], inoutpadout, bottom, 2*xsep, dwid, diffusion);
   fillport (ports[13], inoutpadin, bottom, xsep, mwid, metal);
   fillport (ports[14], outpad, bottom, 0, dwid, diffusion);

   PLACEPADS ('Full Chip', 'Chip', ports, maxport);
end;


{###############################################################################}
{#                                                                             #}
{#      T E S T  15 :  A test of the ILAP symbols for annotation               #}
{#                                                                             #}
{###############################################################################}

Procedure test15;

   Var
      i : integer;
      characters : string [255];

begin
   starttest ('A test of the symbols for annotation');
   characters := '';
   for i := 33 to 126 do begin          { All printable Ascii Characters }
      characters := characters+chr(i);
      if i mod 16 = 0 then characters := characters+chr(10);
   end;

   text ('chars', characters, 850, 700);
   crest ('Crest', 275, 350);
   copyright ('Copyright', 275, 350);

   symbol ('areas');
      layer (red);
      box (275, 0, 550, 350);
      box (0, 700, 850, 1400);
   endsymbol;

   symbol ('annotation');
      draw ('chars', 0, 700);
      draw ('crest', 275, 0);
      draw ('Areas', 0, 0);
   endsymbol;
end;

{###############################################################################}
Begin
   INITIALISE ('PTESTALL');

   test1;
   test2;
   test3;
   test4;
   test5;
   test6;
   test7;
   test8;
   test9;
   test10;
   test11;
   test12;
   test13;
   test14;
   test15;

   starttest ('');
   givestatistics;
   finish;

End.